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1 ? 2008 scillc. all rights reserved characteristics subject to change without notice doc. no. md-1104, rev. g 256-kb i 2 c cmos serial eeprom cat24c256 pin configuration functional symbol features supports standard and fast i 2 c protocol 1.8v to 5.5v supply voltage range 64-byte page write buffer hardware write protection for entire memory schmitt triggers and noise suppression filters on i 2 c bus inputs (scl and sda). low power cmos technology 1,000,000 program/erase cycles 100 year data retention industrial temperature range rohs-compliant 8-pin pdip, soic, tssop and 8-pad tdfn packages pdip (l) soic (w, x) tssop (y) tdfn (zd2) v cc v ss sd a scl wp cat24c256 a 2 , a 1 , a 0 device description the cat24c256 is a 256-kb serial cmos eeprom, internally organized as 32,768 words of 8 bits each. it features a 64-byte page write buffer and supports both the standard (100khz) as well as fast (400khz) i 2 c protocol. write operations can be inhibited by taking the wp pin high (this protects the entire memory). external address pins make it possible to address up to eight cat24c256 devices on the same bus. 8 7 6 5 v cc wp scl sda a 2 a 0 a 1 v ss 1 2 3 4 for the location of pin 1, please consult the corresponding package drawing. pin functions a 0 , a 1 , a 2 device address sda serial data scl serial clock wp write protect v cc power supply v ss ground * catalyst carries the i 2 c protocol under a license from the philips corporation. for ordering information details, see page 15.
cat24c256 2 doc. no. md-1104, rev. g ? 2008 scillc. all rights reserved characteristics subject to change without notice absolute maximum ratings (1) storage temperature -65c to +150c voltage on any pin with respect to ground (2) -0.5 v to +6.5 v reliability characteristics (3) symbol parameter min units n end (4) endurance 1,000,000 program/ erase cycles t dr data retention 100 years d.c. operating characteristics v cc = 1.8 v to 5.5 v, t a = -40c to 85c, unless otherwise speci ed. symbol parameter test conditions min max units i cc supply current read or write at 400khz 1 ma i sb standby current all i/o pins at gnd or v cc 1 a i l i/o pin leakage pin at gnd or v cc 1 a v il input low voltage -0.5 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage v cc 2.5 v, i ol = 3.0ma 0.4 v v ol2 output low voltage v cc < 2.5 v, i ol = 1.0ma 0.2 v pin impedance characteristics v cc = 1.8 v to 5.5 v, t a = -40c to 85c, unless otherwise speci ed. symbol parameter conditions min max units c in (3) sda i/o pin capacitance v in = 0v 8 pf c in (3) input capacitance (other pins) v in = 0v 6 pf i wp (5) wp input current (cat24c256 rev. c - new product) v in < v ih, v cc = 5.5v 200 a v in < v ih, v cc = 3.3v 150 v in < v ih, v cc = 1.8v 100 v in > v ih 1 notes: (1) stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rat ings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sectio ns of this speci cation is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliabil ity. (2) the dc input voltage on any pin should not be lower than -0.5v or higher than v cc + 0.5v. during transitions, the voltage on any pin may undershoot to no less than -1.5v or overshoot to no more than v cc + 1.5v, for periods of less than 20 ns. (3) these parameters are tested initially and after a design or process change that affects the parameter according to appropri ate aec-q100 and jedec test methods. (4) page mode, v cc = 5v, 25c (5) when not driven, the wp pin is pulled down to gnd internally. for improved noise immunity, the internal pull-down is relati vely strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input high. to conserve power, as the input level exceeds the trip point of the cmos input buffer (~ 0.5 x v cc ), the strong pull-down reverts to a weak current source. the variable wp input impedance is available only for die rev. c, new product.
cat24c256 3 doc no. md-1104, rev. g ? 2008 scillc. all rights reserved characteristics subject to change without notice a.c. characteristics (1) v cc = 1.8 v to 5.5 v, t a = -40 c to 85 c, unless otherwise speci ed. symbol parameter standard fast units min max min max f scl clock frequency 100 400 khz t hd:sta start condition hold time 4 0.6 ? s t low low period of scl clock 4.7 1.3 ? s t high high period of scl clock 4 0.6 ? s t su:sta start condition setup time 4.7 0.6 ? s t hd:dat data in hold time 0 0 ? s t su:dat data in setup time 250 100 ns t r (2) sda and scl rise time 1000 300 ns t f (2) sda and scl fall time 300 300 ns t su:sto stop condition setup time 4 0.6 ? s t buf bus free time between stop and start 4.7 1.3 ? s t aa scl low to data out valid 3.5 0.9 ? s t dh data out hold time 100 100 ns t i (2) noise pulse filtered at scl and sda inputs 100 100 ns t su:wp wp setup time 0 0 ? s t hd:wp wp hold time 2.5 2.5 ? s t wr write cycle time 5 5 ms t pu (2, 3) power-up to ready mode 1 1 ms notes: (1) test conditions according to ?a.c. test conditions? table. (2) tested initially and after a design or process change that affects this parameter. (3) t pu is the delay between the time v cc is stable and the device is ready to accept commands. a.c. test conditions input levels 0.2 x v cc to 0.8 x v cc input rise and fall times 50ns input reference levels 0.3 x v cc , 0.7 x v cc output reference levels 0.5 x v cc output load current source: i ol = 3ma (v cc 2.5v); i ol = 1 ma (v cc < 2.5v); c l = 100pf
cat24c256 4 doc. no. md-1104, rev. g ? 2008 scillc. all rights reserved characteristics subject to change without notice power-on reset (por) the cat24c256 die rev. c incorporates power-on reset (por) circuitry which protects the internal logic against powering up in the wrong state. the device will power up into standby mode after v cc exceeds the por trigger level and will power down into reset mode when v cc drops below the por trigger level. this bi-directional por feature protects the device against ?brown-out? failure following a tem- porary loss of power. pin description scl: the serial clock input pin accepts the serial clock generated by the master. sda: the serial data i/o pin receives input data and transmits data stored in eeprom. in transmit mode, this pin is open drain. data is acquired on the positive edge, and is delivered on the negative edge of scl. a 0 , a 1 and a 2 : the address pins accept the device ad- dress. these pins have on-chip pull-down resistors. wp: the write protect input pin inhibits all write op- erations, when pulled high. this pin has an on-chip pull-down resistor. functional description the cat24c256 supports the inter-integrated circuit (i 2 c) bus data transmission protocol, which de nes a device that sends data to the bus as a transmitter and a device receiving data as a receiver. data ow is controlled by a master device, which generates the serial clock and all start and stop conditions. the cat24c256 acts as a slave device. master and slave alternate as either transmitter or receiver. up to 8 devices may be connected to the bus as determined by the device ad- dress inputs a 0 , a 1 , and a 2 . i 2 c bus protocol the i 2 c bus consists of two ?wires?, scl and sda. the two wires are connected to the v cc supply via pull-up resistors. master and slave devices connect to the 2- wire bus via their respective scl and sda pins. the transmitting device pulls down the sda line to ?transmit? a ?0? and releases it to ?transmit? a ?1?. data transfer may be initiated only when the bus is not busy (see a.c. characteristics). during data transfer, the sda line must remain stable while the scl line is high. an sda transition while scl is high will be interpreted as a start or stop condition (figure 1). start the start condition precedes all commands. it consists of a high to low transition on sda while scl is high. the start acts as a ?wake-up? call to all receivers. absent a start, a slave will not respond to commands. stop the stop condition completes all commands. it consists of a low to high transition on sda while scl is high. the stop starts the internal write cycle (when follow- ing a write command) or sends the slave into standby mode (when following a read command). device addressing the master initiates data transfer by creating a start condition on the bus. the master then broadcasts an 8-bit serial slave address. the rst 4 bits of the slave address are set to 1010, for normal read/write opera- tions (figure 2). the next 3 bits, a 2 , a 1 and a 0 , select one of 8 possible slave devices. the last bit, r/w, speci es whether a read (1) or write (0) operation is to be performed. acknowledge after processing the slave address, the slave responds with an acknowledge (ack) by pulling down the sda line during the 9 th clock cycle (figure 3). the slave will also acknowledge the byte address and every data byte presented in write mode. in read mode the slave shifts out a data byte, and then releases the sda line during the 9 th clock cycle. if the master acknowledges the data, then the slave continues transmitting. the master terminates the session by not acknowledging the last data byte (noack) and by sending a stop to the slave. bus timing is illustrated in figure 4.
cat24c256 5 doc no. md-1104, rev. g ? 2008 scillc. all rights reserved characteristics subject to change without notice figure 3. acknowledge timing figure 2. slave address bits figure 1. start/stop timing figure 4. bus timing 1010 device address a 2 a 1 a 0 r/w start condition stop condition sda scl 189 start scl from master bus release delay (transmitter) bus release delay (receiver) data output from transmitter data output from receiver ack delay ( t aa ) ack setup ( t su:dat ) t high scl sda in sda out t low t f t low t r t buf t su:sto t su:dat t hd:dat t hd:sta t su:sta t aa t dh
cat24c256 6 doc. no. md-1104, rev. g ? 2008 scillc. all rights reserved characteristics subject to change without notice write operations byte write in byte write mode the master sends a start, followed by slave address, two byte address and data to be written (figure 5). the slave acknowledges all 4 bytes, and the master then follows up with a stop, which in turn starts the internal write operation (figure 6). during internal write, the slave will not acknowledge any read or write request from the master. page write the cat24c256 contains 32,768 bytes of data, arranged in 512 pages of 64 bytes each. a two byte address word, following the slave address, points to the rst byte to be written. the most signi cant bit of the address word is ?don?t care?, the next 9 bits identify the page and the last 6 bits identify the byte within the page. up to 64 bytes can be written in one write cycle (figure 7). the internal byte address counter is automatically in- cremented after each data byte is loaded. if the master transmits more than 64 data bytes, then earlier bytes will be overwritten by later bytes in a ?wrap-around? fashion (within the selected page). the internal write cycle starts immediately following the stop. acknowledge polling acknowledge polling can be used to determine if the cat24c256 is busy writing or is ready to accept com- mands. polling is implemented by interrogating the device with a ?selective read? command (see read operations). the cat24c256 will not acknowledge the slave address, as long as internal write is in progress. hardware write protection with the wp pin held high, the entire memory is pro- tected against write operations. if the wp pin is left oating or is grounded, it has no impact on the operation of the cat24c256. the state of the wp pin is strobed on the last falling edge of scl immediately preceding the rst data byte (figure 8). if the wp pin is high during the strobe interval, the cat24c256 will not acknowledge the data byte and the write request will be rejected. delivery state the cat24c256 is shipped erased, i.e., all bytes are ffh.
cat24c256 7 doc no. md-1104, rev. g ? 2008 scillc. all rights reserved characteristics subject to change without notice figure 7. page write timing figure 6. write cycle timing a 15 ?a 8 slave address s a c k a c k a c k bus activity: master sda line s t a r t a 7 ?a 0 byte address data n+63 data a c k s t o p a c k data n a c k p a c k * * = don't care bit t wr stop condition start condition address ack 8 th bit byte n scl sda figure 5. byte write timing a 15 ?a 8 slave address s a c k a c k data a c k s t o p p bus activity: master sda line s t a r t a 7 ?a 0 byte address a c k * * = don't care bit figure 8. wp timing 1891 8 a 7 a 0 d 7 d 0 t su:wp t hd:wp address byte data byte scl sda wp
cat24c256 8 doc. no. md-1104, rev. g ? 2008 scillc. all rights reserved characteristics subject to change without notice read operations immediate address read in standby mode, the cat24c256 internal address counter points to the data byte immediately following the last byte accessed by a previous operation. if that ?previ- ous? byte was the last byte in memory, then the address counter will point to the 1 st memory byte, etc. when, following a start, the cat24c256 is presented with a slave address containing a ?1? in the r/w bit position (figure 9), it will acknowledge (ack) in the 9 th clock cycle, and will then transmit data being pointed at by the internal address counter. the master can stop further transmission by issuing a noack, followed by a stop condition. selective read the read operation can also be started at an address different from the one stored in the internal address counter. the address counter can be initialized by per- forming a ?dummy? write operation (figure 10). here the start is followed by the slave address (with the r/w bit set to ?0?) and the desired two byte address. instead of following up with data, the master then issues a 2 nd start, followed by the ?immediate address read? se- quence, as described earlier. sequential read if the master acknowledges the 1 st data byte transmitted by the cat24c256, then the device will continue trans- mitting as long as each data byte is acknowledged by the master (figure 11). if the end of memory is reached during sequential read, then the address counter will ?wrap-around? to the beginning of memory, etc. sequential read works with either ?immediate address read? or ?selective read?, the only difference being the starting byte address.
cat24c256 9 doc no. md-1104, rev. g ? 2008 scillc. all rights reserved characteristics subject to change without notice figure 11. sequential read timing bus activity: master sda line data n+x data n a c k a c k data n+1 a c k s t o p n o a c k data n+2 a c k p slave address figure 10. selective read timing a 15 ? a 8 slave address s a c k a c k a c k bus activity: master sda line s t a r t a 7 ? a 0 byte address slave address s a c k n o a c k s t a r t data p s t o p * * = don't care bit figure 9. immediate address read timing scl sda 8 th bit stop no ack data out 89 slave address s a c k data n o a c k s t o p p bus activity: master sda line s t a r t
cat24c256 10 doc. no. md-1104, rev. g ? 2008 scillc. all rights reserved characteristics subject to change without notice pdip 8-lead 300 mils (l) notes: (1) all dimensions are in millimeters. (2) complies with jedec ms-001. pdip 8-lead 300mils (l) symbol min nom max a 5.33 a1 0.38 a2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 d 9.02 9.27 10.16 e 7.62 7.87 8.25 e 2.54 bsc e1 6.10 6.35 7.11 eb 7.87 10.92 l 2.92 3.30 3.80 for current tape and reel information, download the pdf le from: http://www.catsemi.com/documents/tapeandreel.pdf package outline drawings
cat24c256 11 doc no. md-1104, rev. g ? 2008 scillc. all rights reserved characteristics subject to change without notice soic 8-lead 150 mils (w) notes: (1) complies with jedec speci cation ms-012 dimensions. (2) all linear dimensions are in millimeters. e1 e a a1 h l c e b d pin # 1 identification top view side view end view a 1.35 1.75 a1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 d 4.80 5.00 e 5.80 6.20 e1 3.80 4.00 e 1.27 bsc h 0.25 0.50 l 0.40 1.27 0o 8o symbol min nom max for current tape and reel information, download the pdf t le from: http://www.catsemi.com/documents/tapeandreel.pdf
cat24c256 12 doc. no. md-1104, rev. g ? 2008 scillc. all rights reserved characteristics subject to change without notice soic 8-lead 208 mils (x) notes: (1) complies with eiaj speci cation. (2) all linear dimensions are in millimeters. for current tape and reel information, download the pdf le from: http://www.catsemi.com/documents/tapeandreel.pdf e1 eb side view top view e d pin#1 identification end view a1 a l c symbol min nom max a 2.03 a1 0.05 0.25 b 0.36 0.48 c 0.19 0.25 d 5.13 5.33 e 7.75 8.26 e1 5.13 5.38 e 1.27 bsc l 0.51 0.76 0o 8o
cat24c256 13 doc no. md-1104, rev. g ? 2008 scillc. all rights reserved characteristics subject to change without notice tssop 8-lead 4.4mm (y) a2 e1 e a1 e b d c a top view side view end view 1 l1 l symbol min nom max a 1.20 a1 0.05 0.15 a2 0.80 0.90 1.05 b 0.19 0.30 c 0.09 0.20 d 2.90 3.00 3.10 e 6.30 6.40 6.50 e1 4.30 4.40 4.50 e 0.65 bsc l 1.00 ref l1 0.50 0.60 0.75 1 0 8 for current tape and reel information, download the pdf le from: http://www.catsemi.com/documents/tapeandreel.pdf notes: (1) all dimensions are in milimiters. angles in degrees (2) complies with jedec mo-153.
cat24c256 14 doc. no. md-1104, rev. g ? 2008 scillc. all rights reserved characteristics subject to change without notice tdfn 8-pad 3 x 4.9mm (zd2) for current tape and reel information, download the pdf le from: http://www.catsemi.com/documents/tapeandreel.pdf e d pin #1 identification pin #1 identification dap size 2.6 x 3.3mm detail a d2 a2 a3 a1 a b l e e2 a a1 top view side view bottom view front view detail a symbol min nom max a 0.70 0.75 0.80 a1 0.00 0.02 0.05 a2 0.45 0.55 0.65 a3 0.20 ref b 0.25 0.30 0.35 d 2.90 3.00 3.10 d2 0.90 1.00 1.10 e 4.80 4.90 5.00 e2 0.90 1.00 1.10 e 0.65 typ l 0.50 0.60 0.70 notes: (1) all dimensions are in milimiters. (2) complies with jedec mo-229.
cat24c256 15 doc no. md-1104, rev. g ? 2008 scillc. all rights reserved characteristics subject to change without notice ordering information notes: (1) all packages are rohs-compliant (lead-free, halogen-free). (2) the standard lead nish is nipdau. (3) the device used in the above example is a cat24c256wi-gt3 (soic-jedec, industrial temperature, nipdau, tape & reel). (4) for soic, eiaj (x) package the standard lead nish is matte-tin. this package is available in 2000 pcs/reel, i.e. cat24c256xi-t2. (5) the tdfn 3x4.9mm (zd2) package is available in 2000 pcs/reel, i.e., cat24c256zd2i-gt2. (6) for additional package and temperature options, please contact your nearest on semiconductor sales of ce. prefix device # suffix 24c256 wi product number cat temperature range i = industrial (-40c to +85c) company id package l: pdip w: soic, jedec x: soic, eiaj (4) y: tssop zd2: tdfn (3x4.9mm) (5) g ? lead finish blank: matte-tin (4) g: nipdau t3 tape & reel t: tape & reel 2: 2000/reel (4)(5) 3: 3000/reel
cat24c256 16 doc. no. md-1104, rev. g ? 2008 scillc. all rights reserved characteristics subject to change without notice revision history date revision comments 10/07/05 a initial issue 11/16/05 b update ordering information add tape and reel speci cations 02/02/06 c update ordering information 01/12/07 d update package outlines. add soic, eiaj package outlines update a.c. characteristics. add a.c. test conditions update figures 1, 3 and 4 delete package marking. deleted tape and reel update ordering information 05/08/07 e update features/packages update pin con guration update pin impedance characteristics add power-on reset (por) text update hardware write protection add wp timing (figure 8) (renumbered figures 9 & 11) add 8-lead tssop package outline add 8-pad tdfn 3x4.9mm package outline updated ordering information 08/15/07 f updated pdip, soic, tssop, and tdfn package outline drawings 12-oct-08 g updated soic 8l, 208mil, package outline drawing change logo and ne print to on semiconductor
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